(a) Field of the Invention
The present invention relates to a semiconductor device, particularly to a MIS semiconductor device including a silicided dual-gate electrode.
(b) Description of Related Art
As widely known in the art, with the decrease in power supply voltage in CMOS devices and the following improvement in threshold voltage accuracy in NMOS transistors and PMOS transistors, dual-gate structures are becoming dominant techniques. More specifically, is used a gate electrode made of polysilicon, part of which is doped with n-type impurities for an NMOS transistor and the other part of which is doped with p-type impurities for a PMOS transistor. In such a dual-gate structure, a pn junction is generated if a single polysilicon feature is used as the gate electrode for the NMOS transistor and the PMOS transistor. Accordingly, a silicided gate electrode formed by siliciding a top portion of the polysilicon feature having the pn junction is often used in combination with the dual-gate structure.
In the silicided portion of the polysilicon dual-gate electrode, agglomeration of silicide occurs to cause a physical break with a certain probability. To prevent the break in the silicided portion, several processes have been proposed. Nowadays, however, as chips are integrated higher and higher and the line width of the gate electrode (gate length) is reduced to 0.1 μm or less, the degree of technical difficulty in preventing the break in the silicided portion is extremely high.
Except the case where the break in the silicided portion occurs on the pn junction or polysilicon having low impurity concentration and high resistance, the break in the silicided portion does not directly lead to an electrical break because conductive polysilicon lies immediately below the silicided portion. However, even if the silicided portion is not completely broken, reduction in thickness of the silicided portion increases the resistance, thereby causing a problem of delay in circuit operation.